1. Field of the Invention
The present invention relates in general to the structural configuration of read-only memories (ROM). In particular, this invention relates to the structural configuration of read-only memories having steep trenches and the method of fabricating the same.
2. Technical Background
Read-only memories are widely utilized in digital electronics applications. For example, computer systems including microcomputers and minicomputers use read-only memories for storing fixed software/firmware routines. A read-only memory (ROM) is a fixed, non-volatile memory. Normally, a ROM's memory cells are pre-programmed with specific data at the ROM's manufacturing facility before the ROM is delivered to a customer. The fabrication process for ROM devices is complicated and requires sophisticated processing steps, each of which consumes precious manufacturing time for materials processing and for adjustment of the manufacturing conditions.
The manufacturing process steps for most compatible ROM devices are virtually the same, up to the stage where each ROM is programmed with its respective memory content. Thus, it is possible to manufacture ROM devices to a semifinished stage and store them until they are to be programmed with designated memory contents or data and then promptly delivered to customers upon request. Such "post-programmed" mask ROMs are commonly employed in the art of ROM manufacturing.
Semiconductor device manufacturers strive to reduce the die area of such ROM devices to decrease the manufacturing costs and enhance their competitiveness in the ROM market. However, one configurational constraint associated with conventional ROM devices is the fact that the polysilicon gate regions of a semiconductor ROM device are normally fabricated on the same plane, with such a plane being subject to the spacing limitations imposed by the resolution of the photolithographic process which is used. This resolution restriction makes it difficult to reduce the device die size because spacing between the polysilicon gate regions cannot be reduced effectively. As may be readily appreciated, a semiconductor device occupying a larger die area than desired results in higher manufacturing costs for that particular device.
The construction of a conventional ROM device is illustrated in FIGS. 1a to 1c. The top view presented in FIG. 1a shows a ROM semiconductor device constructed on a substrate 10 (see FIG. 1b or 1c) which may be of, for example, P.sup.- type material. As is better shown in FIGS. 1b and 1c, a plurality of drain/source regions 12 (of, for example, N.sup.+ type material), a gate oxide layer 14, and a plurality of polysilicon gate regions 16 are subsequently formed on the substrate 10.
It should be noted that in the description of this patent, the term "drain/source region" refers to either a drain region or to a source region of the device. Whether the region is a drain or a source is determined by how the device is connected to external metal lines.
In FIG. 1a, a prior art memory cell transistor is outlined generally by dotted-line 18. Such a conventional ROM device configuration must be processed by photoresist masking and ion implantation procedures as shown in FIG. 1c when its memory is to be programmed. First, a photoresist layer 20 is applied and patterned to expose the designated memory cells that will be permanently turned off when programmed. An ion implantation procedure is then conducted to turn off channel 22 permanently in those cells. With the conventional ROM device configuration, the polysilicon gate regions 16 (of the ROM memory cells) are on the same plane of the semiconductor structure. Hence, the miniaturization of semiconductor die size is limited by spacing requirements.
Moreover, the channel 22 also occupies significant semiconductor die surface area of the planar configuration memory cell transistor 18 because the drain/source regions are on the same plane.